library ieee;
use ieee.std_logic_1164.all;

entity shiftRegModule is
	port (
		clk, dataIn, QInPrev, selectH, selectL : in bit;
		R : out bit
	);
end entity shiftRegModule;

architecture STRUCTURAL of shiftRegModule is

	component mux4to1
	
		port (I0, I1, I2, I3, S0, S1 : in bit;
			F : out bit
		);
		
	end component;
	
	component dFlipFlop
	-- clear is active low here
	-- right now we dont use it, so lets make it high
		port(d, clk, clr_al : in bit;
			q, qn : out bit
		);
	
	end component;
	
	for all : mux4to1 use entity work.mux4to1(DATAFLOW);
	for all : dFlipFlop use entity work.dFlipFlop(DATAFLOW);
	
	signal muxOut : bit;
	signal flipFlopOut : bit;
	
begin

	mux : mux4to1 port map(QINPrev, flipFlopOut, dataIn, '0', selectH, selectL,
		muxOut
	);
	
	flipFlop : dFlipFlop port map(muxOut, clk, '1', flipFlopOut);
	
	R <= flipFlopOut;

end architecture STRUCTURAL;
